The present invention relates generally to the manufacture of integrated circuits and more specifically to complementary bipolar transistors having high Early voltage, high frequency performance, and high breakdown voltage characteristics. Evolution of these analog products parallels the industry trend for higher speed semiconductor devices and higher levels of functional integration. Historically, device architectures have been characterized by deep device junctions and have not minimized lateral device geometries. Furthermore, the limited variety of device types which can be fabricated with a given process has, in turn, limited the integration of analog and digital functions.
U.S. Pat. No. 4,665,425 to Piotrowski teaches the fabrication of vertical complementary bipolar transistors in dielectrically isolated islands. By forming vertical NPN and PNP transistors frequencies above 1 GHz have become achievable.
In order to attain higher frequency performance, it is necessary to decrease junction depths and lateral device dimensions. Junction depths can be reduced with self-aligned polysilicon emitters and the emitter-to-extrinsic base spacing can be reduced with an interposing dielectric spacer. A further advantage of polysilicon emitters is that they allow favorable trade-offs between current gain and Early voltage. U.S. Pat. No. 4,908,691 to Silvestri, et al. discloses an exemplary high frequency BiCMOS process. Vertical complementary bipolar transistors are formed in an integrated circuit having lateral dielectric isolation and junction bottom isolation.
It is an object of the present invention to provide a method of fabricating complementary bipolar transistors of still higher frequency.
Another object of the invention is to provide complementary bipolar transistors for high frequency analog applications characterized by increased current gain and Early voltage characteristics.
Still another object is to provide a method for manufacturing integrated circuits incorporating these higher performance complementary bipolar transistors.
According to a preferred embodiment of the invention there is now provided an integrated circuit with complementary bipolar transistors formed in electrically isolated islands having an Early voltage of at least 40 volts; a collector to base breakdown voltage of at least 12 volts; and a frequency response of at least 3 Ghz. Preferably, the transistors exhibit a current gain of at least 100 and a collector to emitter breakdown voltage of at least 12 volts. The base region should have a net peak dopant concentration at least 50 times larger than the net dopant concentration in the collector, and the collector width should be in the range of 0.7 to 1.5 microns. The net peak dopant concentration in the base region should be in the range of 4.times.10.sup.17 cm.sup.-3 to 2.0.times.10.sup.18 cm.sup.-3. The process also enables provision of field effect transistors having a frequency response of at least 4 Ghz.
An integrated circuit can be configured with these transistors to provide a feedback amplifier having a bandwidth of at least 45 Mhz and a slew rate of at least 2,000 volts per micro second. The amplifier will operate at a maximum supply current of 25 milliamps and may be connected in the voltage feedback or current feedback mode.
Sample and hold circuits made with these amplifiers in a voltage feedback configuration will exhibit typical acquisition times on the order of 50 ns, to be compared with prior art 500 ns times for 12 bit resolution. In a current feedback configuration a typical 15 ns acquisition time is achievable at 12 bits of resolution with 200 MHz bandwidth. Typical slew rates of 150 volts per microsecond and 500 volts per microsecond are achievable for voltage and current feedback configurations, respectively. A digital to analog converter comprising transistors of the present invention will exhibit a typical settling time of less than 30 nanoseconds to one-half LSB with at least 11 bit resolution. Switches comprising these transistors will exhibit a rise and fall time of less than one nanosecond. When used with programmable current sources, the switches will produce a program current non-linearity of less than one percent.
The process forms complementary pairs of bipolar transistors each having similar base depths and similar distances from the base to a heavily doped buried collector region. These similar profiles are achieved with complementary impurities having similar diffusion coefficients in the base and buried collector regions. For a silicon process the preferred dopants are phosphorous and boron. Since these species each have an atomic radius smaller than that of silicon, impurity atoms having a larger atomic radius may be added to reduce stress within the active lattice structure. Such an impurity may be arsenic, antimony, or germanium. The concentration of stress reducing impurity is sufficiently low as to not detrimentally affect the net dopant concentration of the buried collector regions.
A double level polysilicon process for making the bipolar transistors is preferred. A first conductor level of polysilicon is selectively doped with impurities which are later outdiffused to the underlying crystal to form extrinsic base regions of the bipolar transistors. The same polysilicon level also forms collector conductors and collector contact regions. The first conductor level is covered with an insulative layer and patterned to expose intrinsic base regions prior to the drive-in. After extrinsic base formation, an insulating layer is formed at least on the exposed base areas and intrinsic base impurities are then introduced.
Lateral spacers are formed on side walls of the first level of conductors and the top insulative layer adjacent the intrinsic base areas to diminish the size of the opening and define the subsequently formed emitter region. The insulative layer on the intrinsic base area separates the spacers from the intrinsic base areas. By forming the spacers after forming the intrinsic base, the extrinsic base to emitter spacing can be increased while maintaining adequate intrinsic base to extrinsic base overlap. The increased emitter to extrinsic base spacing increases current gain and emitter to base breakdown voltage and reduces emitter junction leakage. Preferably, the insulative layer is oxide and the spacers are nitride. This eliminates undercutting of the spacer and provides better control of the extrinsic base to emitter spacing.
The second level of polysilicon is next formed on the wafer. Portions of this second polysilicon layer contacting the intrinsic base areas of the first N and P islands are selectively doped with N and P impurities respectively to form emitter contacts. The impurities are outdiffused from the emitter contacts to form the emitter regions.
The resulting spacer design and impurity profiles provide bipolar transistor structures having high frequency response, high Early voltage, high breakdown voltage and high current gain. The transistors are formed in isolated islands with minimum geometry to maximize density. The impurity concentration of the collector regions is kept low and the lateral dimensions of the emitter, base and collector are minimized.
Additional devices can be formed without requiring additional process steps. For example, a capacitor can be formed wherein the bottom plate is a region of the crystal layer and the top plate is the first polysilicon conductor. Resistors may be formed as thin films or in the substrate itself. JFETs and buried Zener diodes may also be formed without any additional processing steps.